Stacked chip assembly with stiffening layer

ABSTRACT

A microelectronic subassembly  210  includes a substrate  215  having a top surface  216  and at least one peripheral region  219,  a microelectronic element  201  mounted over the substrate  215,  a plurality of leads  218, 222  electrically connected to the microelectronic element  201  having outer ends overlying the at least one peripheral region  219  of the substrate  215,  and vertical conductors  208  electrically connected with the outer ends of the leads. The subassembly includes an encapsulant layer  204  provided over the top surface  216  of the substrate  215  and around the microelectronic element  201  and the vertical conductors  208  for stiffening the substrate  215  at the at least one peripheral region  219  of the substrate for facilitating handling and testing of the subassembly.

TECHNICAL FIELD

The present invention generally relates to stacked microelectronicassemblies, and more particularly relates to stacked microelectronicassemblies having a stiffening layer.

BACKGROUND ART

In certain preferred embodiments of commonly assigned U.S. Pat. No.5,861,666, the disclosure of which is hereby incorporated by referenceherein, a stacked microelectronic assembly includes a plurality of chipand interposer subassemblies. Each subassembly has a circuitizedinterposer and a semiconductor chip, one face of which confronts asurface of the interposer. Each interposer has at least one peripheralregion projecting laterally beyond an edge of the chip mounted to theinterposer. Each interposer also includes a plurality of leadselectrically connected to contacts on the chip face that extend to theperipheral region of the interposer. The subassemblies are stacked oneatop another in a generally vertical configuration so that the chipsoverlie one another and so that the projecting portions of theinterposers overlie one another. The subassemblies are electricallyconnected one to another by vertical conductors extending alongside thechips and interconnecting the leads of the various interposers at theirperipheral regions.

FIG. 1A shows a microelectronic assembly 100 disclosed in U.S. Pat. No.5,861,666 made from a number N of prefabricated subassemblies,comprising N−1 subassemblies 110 and base subassembly 120. Subassembly110 comprises a semiconductor chip 101 having opposed surfaces 102 and103, one surface having exposed electrical contacts (not shown), and aninterposer 115 having a first surface 116 and a second surface 117.Interposer 115 is preferably a flexible sheet-like element. Chip 101 ismounted on first surface 116 of interposer 115 and the contacts areelectrically connected to conductors (not shown) on a surface ofinterposer 115. Fan-out connectors 111, such as high-melting temperaturesolder balls, are affixed to the second surface 117 of the interposer115 (the side opposite chip 101). In each subassembly 110, theelectrical connections between chip 101 and interposer 115 areencapsulated in a material 104 such as an epoxy or elastomer, whichfills the gaps between chip 101 and surface 116 and partially surroundsthe chip. The base subassembly 120 comprises an encapsulatedmicroelectronic element 101, encapsulant 104 and interposer 125 similarto those described above for subassembly 110. A plurality of joiningunits 121 are affixed to second surface 127 (the side opposite frommicroelectronic element 101) of interposer 125. Base subassembly 120 isadapted to serve as the bottom-most unit of stack 100 and may be affixeddirectly to an external element such as a printed circuit board or asecond microelectronic assembly.

When subassemblies 110 and 120 are stacked, fan-out connectors 111electrically interconnect the subassemblies within the stack, therebyacting as vertical conductors. To allow stacking, fan-out connectors 111of each subassembly 110 must be positioned outside of the region ofinterposer 115 of the next lower subassembly occupied by chip 101 andencapsulant 104. Typically, this requirement results in fan-outconnectors 111 of each subassembly 110 being disposed in a peripheralregion of interposer 115 which is not covered by encapsulant 104 onfirst surface 116. This peripheral region, therefore, remains quiteflexible, which may lead to difficulties in handling the subassembliesand in bonding the fan-out connectors when the subassemblies arestacked. The subassemblies can be made more rigid by dispensingadditional encapsulant as shown in FIG. 2A. Increasing the area coveredby encapsulant reduces the area available for the fan-out connectors,thereby decreasing the number of rows of connectors that may be used andresulting in poor utilization of the interposer. The problems arisingfrom excessive flexing of the peripheral regions are even morepronounced where multiple rows of fan-out connectors or joining unitsare employed (FIG. 2B) and where a differently sized die is used in theupper subassemblies (FIG. 2C).

In spite of the advances set forth in U.S. Pat. No. 5,861,666, thereremains a need for a stackable microelectronic subassembly that iseasily handled and tested during making of a stacked microelectronicassembly. There also remains a need for a stackable microelectronicsubassembly having a stiffening layer for stiffening peripheral regionsof the subassembly. The present invention addresses these needs.

SUMMARY OF THE INVENTION

In accordance with certain preferred embodiments of the presentinvention, a microelectronic subassembly includes a substrate, such as aflexible dielectric substrate, having a top surface and at least oneperipheral region, a microelectronic element mounted over the substrate,and a plurality of leads electrically connected to the microelectronicelement having outer ends overlying the at least one peripheral regionof the substrate. The subassembly also desirably includes verticalconductors, such as solder balls, electrically connected with the outerends of the leads, and an encapsulant layer provided over the topsurface of the substrate and around the microelectronic element and thevertical conductors for stiffening the substrate at the at least oneperipheral region of the substrate. In certain embodiments, thesubstrate may be a flexible substrate made of a polymeric material.

In certain preferred embodiments, the microelectronic element is asemiconductor chip having a front face with contacts and a back faceremote therefrom. The semiconductor chip may be assembled with thesubstrate so that the front face of the semiconductor chip faces the topsurface of the substrate with the leads connected to the chip contacts.In other preferred embodiments, the semiconductor chip may be assembledwith the substrate so that the back face of the semiconductor chipconfronts the top surface of the substrate and the front face faces awayfrom the substrate. In this particular embodiment, the subassembly mayinclude conductive wires having first ends connected to the chipcontacts and second ends connected to the leads.

The subassembly also preferably includes a compliant layer disposedbetween the microelectronic element and the substrate so as to permitrelative movement of the microelectronic element and the substrateduring thermal cycling of the subassembly. The compliant layer mayinclude a plurality of compliant pads spaced from one another fordefining channels or gaps therebetween. The stiffening encapsulant layermay be disposed in the channels between the compliant pads.

The stiffening encapsulant layer is preferably selected from the groupconsisting of flexibilized epoxies, silicone elastomers, glass sheet,glass-filled epoxies, ceramic materials and plastics. Although thepresent invention is not limited by any particular theory of operation,it is believed that providing a stiffening layer that surrounds thevertical conductors in the peripheral region of the substrate willenhance handling and testability of the subassembly by providingsufficient stiffness in the peripheral region of the subassembly. Absentthe stiffener layer, the peripheral region of the substrate may flex,bend or flop to an undesirable degree during testing and handling.

In certain preferred embodiments, the substrate includes a plurality ofdielectric layers, and a plurality of layers of conductive tracesextending through the substrate. The substrate may also include aconductive metal layer adapted to function as a power plane. In yetother preferred embodiments, the substrate may also include a conductivemetal layer adapted to function as a ground plane.

In other preferred embodiments of the present invention, amicroelectronic subassembly includes a substrate having a top surface, abottom surface and at least one peripheral region, a microelectronicelement mounted over the top surface of the substrate, and a pluralityof leads electrically connected to the microelectronic element, theleads having outer ends overlying the at least one peripheral region ofthe substrate. The microelectronic subassembly also preferably includesvertical conductors electrically connected with the outer ends of theleads, and an encapsulant layer provided over one of the surfaces of thesubstrate and around the vertical conductors for stiffening the at leastone peripheral region of the substrate. In certain preferredembodiments, the vertical conductors are disposed over the bottomsurface of the substrate and the stiffening encapsulant layer isprovided over the bottom surface of the substrate and around thevertical conductors.

In yet further preferred embodiments of the present invention, amicroelectronic assembly includes a plurality of microelectronicsubassemblies, each subassembly having a substrate with at least oneperipheral region, a microelectronic element mounted over the substrate,a plurality of leads electrically connected to the microelectronicelement having outer ends overlying the at least one peripheral regionof the substrate, vertical conductors electrically connected with theouter ends of the leads, and an encapsulant layer provided over asurface of the substrate and around the vertical conductors forstiffening the substrate at the least one peripheral region of thesubstrate. The microelectronic subassemblies are stacked one atopanother and electrically interconnected through the vertical conductors.The vertical conductors preferably form electrical interconnectionsbetween leads of different subassemblies. The vertical conductorspreferably include metallic masses, such as solder balls. Themicroelectronic elements of the assembly may vary in size.

In certain preferred embodiments, each of the substrates has a centralregion aligned with the microelectronic element mounted thereto and aplurality of peripheral regions extending outwardly at a plurality ofedges of the substrate.

These and other preferred embodiments of the present invention will bedescribed in more detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a conventional stacked microelectronic assembly.

FIG. 1B shows an upper layer of the stacked microelectronic assembly ofFIG. 1A.

FIG. 1C shows a base layer of the stacked microelectronic assembly ofFIG. 1A.

FIG. 2A shows another conventional stacked microelectronic assembly.

FIG. 2B shows still another conventional stacked microelectronicassembly.

FIG. 2C shows yet another conventional stacked microelectronic assembly.

FIG. 3A shows a stacked microelectronic assembly including stiffeninglayers, in accordance with certain preferred embodiments of the presentinvention.

FIG. 3B shows an upper layer of the stacked microelectronic assembly ofFIG. 3A.

FIG. 3C shows a base layer of the stacked microelectronic assembly ofFIG. 3A.

FIG. 4A shows an enlarged fragmentary view of the stackedmicroelectronic assembly of FIG. 3A.

FIG. 4B shows another enlarged fragmentary view of FIG. 4A in accordancewith certain preferred embodiments of the present invention.

FIG. 4C shows still another enlarged fragmentary view of FIG. 4A.

FIG. 5A shows a stacked microelectronic assembly with stiffening layers,in accordance with yet other preferred embodiments of the presentinvention.

FIG. 5B shows a stacked microelectronic assembly with stiffening layers,in accordance with further preferred embodiments of the presentinvention.

FIGS. 6A and 6B show perspective views of a stacked microelectronicassembly with stiffening layers during various phases of the assemblyprocess, in accordance with certain preferred embodiments of the presentinvention.

FIG. 7A shows a stacked microelectronic assembly with one or morestiffening layers, in accordance with still other preferred embodimentsof the present invention.

FIG. 7B shows an upper subassembly layer of the stacked microelectronicassembly of FIG. 7A.

FIG. 7C shows a base layer of the stacked microelectronic assembly ofFIG. 7A.

FIG. 8 shows a stacked microelectronic assembly with one or morestiffening layers, in accordance with other preferred embodiments of thepresent invention.

FIG. 9 shows a stacked microelectronic assembly with one or morestiffening layers, in accordance with still other preferred embodimentsof the present invention.

FIG. 10 shows a stacked microelectronic assembly with stiffening layers,in accordance with still further preferred embodiments of the presentinvention.

BEST MODE OF CARRYING OUT INVENTION

FIG. 3A illustrates a preferred embodiment of the stacked assembly ofthe present invention. Stacked assembly 200 includes a plurality of N−1subassemblies 210 stacked one atop another with a base subassembly 220occupying the bottom-most position in the stack. Referring to FIGS. 3Band 3C, each subassembly 210, 220 includes a microelectronic element201, such as a semiconductor chip, having a front face 202, a back face203 opposite front face 202 and a plurality of contacts 205 exposed atfront face 202. Preferably, contacts 205 are exposed in a peripheralregion of the chip face. Interposer 215 is desirably a dielectricelement having a first surface 216, a second surface 217 opposite firstsurface 216 and a plurality of conductive pads (not shown) disposed onfirst surface 216. Interposer 215 also preferably has conductiveelements 218 such as metallic traces thereon, with contacts 205 of chip201 being electrically connected to conductive elements 218. Preferably,interposer 215 is made of a flexible dielectric material such aspolyimide tape. Interposer 215 may also include one or more additionallayers such as a conductive metal layer to serve as a power or groundplane, multiple layers of traces and multiple dielectric layers.

Referring to FIGS. 3B and 3C, the electrical connection between thecontacts on face surface 202 and the pads on first surface 216 may bemade by any of the known methods of making electrical connectionsincluding, but not limited to, flip-chip bonding, wire bonding, tabbonding and the bonding methods disclosed in commonly assigned U.S. Pat.Nos. 5,148,265; 5,148,266; 5,518,964 and 5,536,909, the disclosures ofwhich are incorporated herein by reference. Preferably, at least one padis movable with respect to at least one contact. The preferredembodiments of the present invention are not limited to the illustratedflip-chip configuration where face surface 202 faces first surface 216of interposer 215. The present invention also contemplates “face-up”configurations, wherein a face surface 202 of a chip faces away frominterposer 215. The utilization of lead-bonding methodologies disclosedin the U.S. Patents cited above are preferred because the resulting leadstructures allow the formation of subassemblies having a very lowoverall height.

Referring to FIGS. 3B and 3C, fan-out connectors 208, such ashigh-melting solder balls, are disposed on first surface 216 ofinterposer 215 and are electrically connected to at least some ofconductive elements 218 on first surface 216. Fan-out connectors 208 arelocated so that, when subassemblies 210, 220 are stacked one atopanother, fan-out connectors 208 electrically interconnect thesubassemblies within the stack, acting as vertical conductors. Fan-outconnectors 208 are preferably located around outer edges of chip 201 andadjacent peripheral regions of interposer 215.

Subassemblies 210, 220 also include respective stiffening layers 204.Each stiffening layer 204 is preferably made of an encapsulatingmaterial, such as a flexibilized epoxy or silicone elastomer, whichsurrounds both microelectronic element 201 and fan-out connectors 208.The encapsulant also desirably encapsulates the leads or other bondingstructures 222 connecting contacts 205 of chip 201 to the conductiveelements of interposer 215.

Referring to FIG. 3C, subassembly 220 also preferably includes joiningunits 228 that are disposed on second surface 217 of interposer 215 andelectrically connected to at least some of the pads on first surface216. Joining units 228 may be used to attach assembly 200 to electricalcontacts or pads on an external electronic element, such as those on aprinted circuit board, or a second microelectronic assembly.

As illustrated in FIG. 4A, a joining unit may be formed by attaching aeutectic solder ball 228 to a conductive pad 229 affixed to secondsurface 217 of interposer 215. Preferably, peripheral region 206 ofinterposer 215 is penetrated by vias 226. Vias 226 may be open at bothends or closed at one end to accommodate various methods of makingelectrical connections, as are known in the art. Vias 226 may beelectrically conductive. Referring to FIG. 4B, in certain preferredembodiments, interposer 235 is formed with openings 239 therein, andsolder mass 239 is allowed to flow into an opening 238 to establishelectrical contact with first surface 236. The embodiment of FIG. 4Ballows interposer 235 to be constructed with a single metallic tape at asubstantially lower cost than the embodiment of FIG. 4A, for which abimetallic tape would more typically be employed.

Referring to FIG. 4A, each subassembly preferably includes fan-outconnectors 208, such as high-temperature solder balls, bonded toconductive elements 218. The diameter of each connector 208 is greaterthan the combined thicknesses of compliant layer 212 and microelectronicelement 201 so that fan-out connector 208 extends beyond chip 201 tocontact via 226 of the subassembly above it. Preferably, back surface203 of chip 201 is in close proximity to second surface 217 of itsadjacent subassembly. A layer 212 of compliant material such as a gel oran elastomer is disposed between front face 202 of each chip 201 andsurface 216 of interposer 215. Thus, interposer 215 of each subassembly210, 220 is mechanically decoupled from chip 201 and free to deform anddeflect independent of the chip. Fan-out connectors 208 may be providedas conventional “solid-core solder balls”, initially having coatings ofsolder which reflow to bond the connectors 208 to vias 226 and,preferably, to contact conductive elements 218.

Referring to FIG. 4A, stiffening layer 204 is provided over top surface216, preferably surrounding microelectronic element 201 and fan-outconnector 208. Preferably, stiffening layer 204 is formed of anencapsulant, more preferably, of a flexibilized epoxy or siliconeelastomer. In certain preferred embodiments, the encapsulant ofinterposer 215 fills gaps between the front face 202 of chip 201 and topsurface 216 of interposer 215, and encapsulates leads 222.

Referring to FIGS. 4A and 4C, microelectronic element 201 is mounted tosurface 206 of interposer 215 in a “face-down” arrangement, that is,where the face surface 202 of element 201 confronts surface 206. Leads222 electrically connect conductive elements 218 to contacts 205. Inpreferred embodiments, leads 222 are flexible leads, preferably formedof copper, gold, alloys thereof and combinations thereof. For example,leads 222 may be formed according to the methods disclosed in commonlyassigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,787,581 and 5,977,618.Referring to FIG. 4C, lead 222 a initially extends over slot 224. Lead222 a may have a notch or other weakened portion that provides afracture point 223 in the lead. A tool may be inserted into slot 224 tobreak lead 222 a and push it to the position of lead 222, making contactwith a contact 205 on chip face 202.

The embodiment of FIG. 4A can readily be modified for “face-up”configurations, that is, the contact-bearing face of the chip faces awayfrom interposer 215, and that contacts 205 can be electrically connectedto terminals on a surface of interposer 215 by wire bonding, flip-chipbonding, tab bonding, or other means of electrical bonding presentlyknown in the art. Moreover, it will be obvious to those skilled in theart that an interposer may be fabricated without a conductive element218 and that lead 222 may be fabricated so as to electrically connect aterminal on a surface of the interposer to a contact on chip face 202.

Referring to FIG. 4A, each subassembly 210, 220 preferably includes aspacer layer 212 disposed between front face 202 of microelectronicelement 201 and interposer 215. Spacer layer 212 is preferablycompliant. Preferred materials for the spacer layers 212 include epoxiesand silicones, with flexibilized epoxies and silicone elastomers beingparticularly preferred. Spacer layer 212 may comprise a single pad ofmaterial, as depicted in FIG. 4A, or a plurality of such pads. Thespacer layer 212 absorbs the stress of differential thermal expansion ofinterposer 215 and the microelectronic element 201 and inhibitsdeformation of the flexible dielectric structure during handling andinstallation of the subassembly. Spacer layer 212 is preferablypositioned to avoid obstructing movement of flexible leads 222 orinterfering with contact between lead 222 and electrical contact 205. Inanother preferred embodiment of the invention, only the base subassembly220 of the stacked microelectronic assembly is provided with a compliantspacer layer 212, as the effects of differential thermal expansiontypically are most critical at the bottom-most subassembly in the stack.

Referring to FIG. 4A, the individual subassemblies 210, 220 arefabricated as described above. Each subassembly 210, 220 may be testedseparately by engaging vias 226 with contacts of a test socket, or byengaging fan-out connector 208 in a socket. The chip 201, leads 222 andconnections can then be tested by actual operation of the chip. Aftertesting, the individual subassemblies 210, 220 are stacked one atopanother so that chips 201 generally overlie one another in front face torear face disposition, and so that peripheral regions 206 of the variousinterposers 215 are aligned with one another. In this arrangement, vias226 of the various interposers 215 and the fan-out connectors 208associated therewith are also aligned one with another. Thus, theconnector 208 associated with its respective via 226 on one interposermakes contact with a corresponding via 226 on the next interposer in thestack.

Referring to FIG. 4A, joining units 228, such as solder balls, aredisposed on second surface 217 of the bottom-most interposer 215 and areelectrically connected to at least some conductive elements 218 on firstsurface 216. Joining units 228 may be used to attach the stackedmicroelectronic assembly to electrical circuit contacts or pads on aprinted circuit board or a second microelectronic assembly.

Referring to FIG. 6A, microelectronic elements 601 are attached to astrip of interposer 615 and electrically connected to the interposer asdescribed herein, and fan-out connectors 608 are affixed to surface 616of interposer 615 as described herein. Referring to FIG. 6B, anencapsulant, such as a flexibilized epoxy or silicone elastomer, isprovided over top surface 616 of interposer 615 to surroundmicroelectronic element 601 and fan-out connectors 608.

Referring to FIGS. 7A-7C, fan-out connectors 708 are affixed to secondsurface 717 of interposer 715. Stiffening layer 704 is joined to secondsurface 717 so as to surround fan-out connectors 708. Stiffening layer704 includes a depression or opening 705 formed therein so that whensubassemblies 710, 720 are stacked one atop another, the respectiveencapsulated chip 711, 721 of the lower subassembly 711, 721 fits withinthe opening 705 of the upper assembly. In the embodiment shown, thebottom subassembly 720 in the stack 700 is fabricated without fan-outconnectors. Subassembly 720 may be provided with joining units 728 ofthe types discussed herein for other embodiments of the presentinvention.

Although FIGS. 3A, 4A and 7A depict embodiments wherein the centers ofthe microelectronic elements are aligned with each other, the presentinvention also includes embodiments wherein at least one microelectronicelement overlies other microelectronic elements in such a way that thecenters of such elements are not aligned. Moreover, the microelectronicelements of the present invention are not limited to singlesemiconductor chips. Alternatively, a plurality of semiconductor chipsmay be laid side by side along the first surface of the interposer orstacked one atop another within a subassembly without departing from theinvention herein disclosed.

In still other preferred embodiments, other electrically conductiveelements may be utilized for creating vertical electrical connectionsbetween the subassemblies within a stack. For example, referring to FIG.4A, vias 226 may serve as fan-out connectors in embodiments whereelectrically conductive vias 226 are aligned one with another, with anelectrically conductive rod inserted through the aligned vias 226 toprovide the electrical interconnection between the subassemblies.Alternatively, other methods of establishing vertical electricalconnections, such as those disclosed in commonly assigned U.S. Pat. No.5,861,666, may be used without departing from the scope of theinvention. In all such embodiments, stiffening layer 204 would bemodified as needed to allow electrical connections to be formedaccording to the connection method used.

The stiffening layer 204 may be may be formed from materials other thanthe encapsulants discussed herein. For example, suitable materialsinclude, but are not limited to, glass sheet, glass-filled epoxy,ceramic materials, or a plastic sheet, so long as the stiffening layersurrounds the microelectronic elements in the central region of theinterposer and the fan-out connectors in the peripheral regions of theinterposer. Alternatively, the stiffening layer may be formed from epoxyor elastomer materials that have a modulus different from the modulus ofthe materials used to encapsulate leads 222 or to form compliant layer212.

Although the present invention is not limited by any particular theoryof operation, it is believed that providing a stiffening layer on theinterposer surface creates a subassembly that is more rigid than thosefabricated by methods currently in use, but which still provides someflexibility in the subassembly design. A stiffening layer that surroundsthe microelectronic element and/or fan-out connectors further increasesthe rigidity of the resulting structure. The methods of the presentinvention may be used to fabricate subassemblies with single or multiplerows of overhung fan-out connectors such as the embodiment of FIG. 5A,or with dies of differing sizes, such as the embodiment of FIG. 5B.

Referring to FIGS. 3B and 3C, each subassembly 210, 220 preferably has aheight or thickness that is about 1 millimeter or less. In morepreferred embodiments, the subassembly has a thickness of about 700microns or less. The preferred lead structures, such as leads 222, havea height of 500 microns or less. Such vertically extensive leads allowthe contacts on the chip face to move relative to the pads on the firstsurface of the dielectric element in response to differences in thermalexpansion among the elements of the assembly. The stiffening layer 204provides the desired stiffness without adding additional height to thesubassembly.

The stacked assembly of the present invention can be fabricated usingreadily available techniques. The assembly preferably provideselectrically conductive pathways connecting the chips in the stack toone another and to external circuit elements with low impedance andshort circuit path lengths, while minimizing mechanical stresses causedby differences in thermal expansion between the chip and the dielectricelements. The presence of stiffening layers in one or more of thesubassemblies result in a more rigid structure than stacked assembliesformed by techniques presently in use.

Referring to FIG. 8, in accordance with another preferred embodiment ofthe present invention, a stacked microelectronic assembly 800 includes afirst subassembly 810 stacked atop and electrically interconnected witha second subassembly 820. The first subassembly includes a flexiblesubstrate 815 having a first surface 816 and a bottom surface 818 remotetherefrom. First subassembly 810 also includes conductive elements 818,such as conductive traces provided over the top surface 816 of flexiblesubstrate 815. First subassembly 810 also includes a microelectronicelement 801, such as a semiconductor chip, including a front contactbearing face 802 and back face 803 remote therefrom. During assembly,microelectronic element 801 is mounted above the top surface 816 offlexible substrate 815 with back face 803 facing top surface 816. Themicroelectronic element 801 is electrically interconnected withconductive element 818 by wire bonds 822. Preferably, wire bonds 822have first ends 823 attached to contacts (not shown) on front face 802of microelectronic element 801 and second ends 824 attached toconductive element 818. Pan-out connectors 808, such as high-meltingtemperature solder balls, are disposed on top surface 816 of flexiblesubstrate 815 and are electrically connected with at least some of theconductive elements 818 extending over top surface 816. The fan-outconnectors 808 are preferably located atop the surface 816 of flexiblesubstrate 815 so that when the subassemblies 810, 820 are stacked oneatop another, the fan-out connectors 808 electrically interconnect thesubassemblies within the stack, thereby acting as vertical conductors.In preferred embodiments, the fan-out connectors 808 extend beyond theouter edges of the microelectronic element 801. In highly preferredembodiments, the fan-out connectors 808 are located adjacent peripheralregions 825 of the flexible substrate 815.

Subassembly 810 also preferably includes a stiffening layer 804 made ofan encapsulating material. In preferred embodiments, the stiffeninglayer 804 is made of an encapsulating material such as flexibilizedepoxy or silicone elastomers, which surround both microelectronicelement 801 and fan-out connectors 808. The stiffening layer 804 mayalso encapsulate the wire bonds 822. In certain preferred embodiments,the stiffening layer completely encapsulates the wire bonds 822 and themicroelectronic element 801. In other embodiments, however, such as theone shown in FIG. 8, the stiffening layer encapsulates only certainsections of the wire bond 822.

Stacked microelectronic assembly 800 also includes second subassembly820 having flexible substrate 815′, microelectronic element 801′,fan-out connectors 808′, wire bonds 822′ and stiffening layer 804′. Inthe particular embodiment shown in FIG. 8, second subassembly 820 issubstantially similar to first subassembly 810. As with the firstsubassembly 810, the stiffening layer 804′ of second subassembly 820adds rigidity to the subassembly in the vicinity of the peripheralregion 825′ of flexible substrate 815′.

Stacked microelectronic assembly 800 also includes one or more joiningunits 828′ provided over second surface 818′ of flexible substrate 815′.The joining units 828′ are preferably electrically interconnected to atleast some of the fan-out connectors 208 and/or microelectronic elements801, 801′. Joining units 828′ are preferably used to attach the stackedmicroelectronic assembly to an external element, such as a substratehaving electrical contacts or pads.

FIG. 9 shows a stacked microelectronic assembly 900, in accordance withanother preferred embodiment of the present invention, including firstsubassembly 910 stacked over second subassembly 920. First subassembly910 includes substrate 915 having top surface 716 and microelectronicelement 901 having back face 903 facing top surface 716. The front fact902 faces away from top surface 916 and has contacts (not shown) thatare electrically interconnected with conductive elements 919 by wirebonds 922. First subassembly 910 includes fan-out connectors 909 atperipheral regions 925 of flexible substrate 915. First subassembly 910also includes a stiffening layer 904 that extends around microelectronicelement 901 and fan-out connectors 909.

Second subassembly 920 includes microelectronic element 901′ having acontact bearing front face 902′ that faces top surface 916′ of flexiblesubstrate 915′. The mounting of the microelectronic element 901′ overflexible substrate 915′ is commonly referred to as a “flip-chip”assembly. The microelectronic element 901′ is electricallyinterconnected with conductive elements 919′ extending over firstsurface 916′ using flexible leads 922′.

FIG. 10 shows a stacked microelectronic assembly 1000 including a firstsubassembly 1010 stacked over a second subassembly 1020. Firstsubassembly 1010 includes a microelectronic element 1001 having acontact bearing face 1002 facing away from top surface 1016 of flexiblesubstrate 1015. Microelectronic element 1001 is electricallyinterconnected with conductive elements 1018 by wire bonds 1022. Firstsubassembly 1010 includes fan-out connectors 1008 provided in peripheralregions 1025 of flexible substrate 1015. A stiffening layer 1004surrounds microelectronic element 1001 and fan-out connectors 1008 forproviding stiffening at peripheral regions 1025 of flexible substrate1015, thereby facilitating testing and handling of the subassembly.

Second subassembly 1020 includes generally similar elements as thosedescribed above in first subassembly 1010, however, second subassembly1020 includes a microelectronic element 1001′ that is substantiallylarger than microelectronic element 1001 of first subassembly 1010.

Although the invention herein has been described with reference toparticular embodiments, it is to be understood that these embodimentsare merely illustrative of the principles and applications of thepresent invention. It is therefore to be understood that numerousmodifications may be made to the illustrative embodiments and that otherarrangements may be devised without departing from the spirit and scopeof the present invention as described herein. Such changes would includethe incorporation of features of the stacked microelectronic assembliesdisclosed in U.S. Pat. No. 5,861,666 or commonly owned U.S. Pat. Nos.6,121,676 and 6,225,688 and commonly assigned U.S. patent applicationSer. No. 09/776,356, the disclosures of which are incorporated herein byreference.

Industrial Applicability

The present invention has applicability in the microelectronicsindustry.

1. A microelectronic subassembly comprising: a substrate having a topsurface and at least one peripheral region; a microelectronic elementmounted over the substrate; a plurality of leads electrically connectedto the microelectronic element having outer ends overlying the at leastone peripheral region of the substrate; vertical conductors electricallyconnected with the outer ends of the leads; an encapsulant layerprovided over the top surface of the substrate and around themicroelectronic element and the vertical conductors for stiffening thesubstrate at the at least one peripheral region of the substrate.
 2. Thesubassembly as claimed in claim 1, wherein the substrate is flexible. 3.The subassembly as claimed in claim 2, wherein the flexible substratecomprises a dielectric material.
 4. The subassembly as claimed in claim2, wherein the flexible substrate comprises a polymeric material.
 5. Thesubassembly as claimed in claim 1, wherein the microelectronic elementis a semiconductor chip having a front face with contacts and a backface remote therefrom.
 6. The subassembly as claimed in claim 5, whereinthe front face of the semiconductor chip faces the top surface of thesubstrate and the leads are connected to the chip contacts.
 7. Thesubassembly as claimed in claim 5, wherein the back face of thesemiconductor chip faces the top surface of the substrate, and whereinthe subassembly further comprises conductive wires having first endsconnected to the chip contacts and second ends connected to the leads.8. The subassembly as claimed in claim 1, further comprising a compliantlayer disposed between the microelectronic element and the substrate soas to permit relative movement of the microelectronic element and thesubstrate during thermal cycling of the subassembly.
 9. The subassemblyas claimed in claim 8, wherein the compliant layer comprises a pluralityof compliant pads spaced from one another, the spaced compliant padsdefining channels therebetween.
 10. The subassembly as claimed in claim9, wherein the stiffening encapsulant layer is disposed in the channelsbetween the compliant pads.
 11. The subassembly as claimed in claim 1,wherein the stiffening encapsulant layer is selected from the groupconsisting of flexibilized epoxies, silicone elastomers, glass sheet,glass-filled epoxy, ceramic materials and plastic.
 12. The subassemblyas claimed in claim 1, wherein the substrate comprises a plurality ofdielectric layers, and wherein a plurality of layers of conductivetraces extend through the substrate.
 13. The subassembly as claimed inclaim 1, wherein the substrate includes a conductive metal layer adaptedto function as a power plane.
 14. The subassembly as claimed in claim 1,wherein the substrate includes a conductive metal layer adapted tofunction as a ground plane.
 15. A microelectronic subassemblycomprising: a substrate having a top surface, a bottom surface and atleast one peripheral region; a microelectronic element mounted over thetop surface of the substrate; a plurality of leads electricallyconnected to the microelectronic element having outer ends overlying theat least one peripheral region of the substrate; vertical conductorselectrically connected with the outer ends of the leads; an encapsulantlayer provided over one of the surfaces of the substrate and around thevertical conductors for stiffening the at least one peripheral region ofthe substrate.
 16. The subassembly as claimed in claim 15, wherein thevertical conductors are disposed over the bottom surface of thesubstrate.
 17. A microelectronic assembly including a plurality ofmicroelectronic subassemblies, each the subassembly comprising: asubstrate having at least one peripheral region; a microelectronicelement mounted over the substrate; a plurality of leads electricallyconnected to the microelectronic element having outer ends overlying theat least one peripheral region of the substrate; vertical conductorselectrically connected with the outer ends of the leads; an encapsulantlayer provided over a surface of the substrate and around the verticalconductors for stiffening the substrate at the at least one peripheralregion of the substrate, wherein the microelectronic subassemblies arestacked one atop another and electrically interconnected through thevertical conductors.
 18. The microelectronic assembly as claimed inclaim 17, wherein the substrates are flexible dielectric substrates. 19.The microelectronic assembly as claimed in claim 17, wherein thevertical conductors form interconnections between leads of differentsubassemblies.
 20. The microelectronic assembly as claimed in claim 17,wherein the vertical conductors comprise metallic masses.
 21. Themicroelectronic assembly as claimed in claim 20, wherein each thesubstrate has a central region aligned with the microelectronic elementmounted to such flexible substrate and a plurality of peripheral regionsextending outwardly at a plurality of edges of each such substrate. 22.The microelectronic assembly as claimed in claim 17, wherein themicroelectronic element is a semiconductor chip having a front face withcontacts and a back face remote therefrom.
 23. The microelectronicassembly as claimed in claim 22, wherein the front face of thesemiconductor chip faces a top surface of the substrate and the leadsare connected to the chip contacts.
 24. The microelectronic assembly asclaimed in claim 22, wherein the back face of the semiconductor chipfaces a top surface of the substrate and wherein the subassembly furthercomprises conductive wires having first ends connected to the chipcontacts and second ends connected to the leads.
 25. The microelectronicassembly as claimed in claim 17, further comprising a compliant layerdisposed between the microelectronic element and the substrate so as topermit relative movement of the microelectronic element and thesubstrate during thermal cycling of the subassembly.
 26. Themicroelectronic assembly as claimed in claim 25, wherein the compliantlayer comprises a plurality of compliant pads spaced from one anotherfor defining channels therebetween.
 27. The microelectronic assembly asclaimed in claim 26, wherein the stiffening encapsulant layer isdisposed in the channels between the compliant pads.
 28. Themicroelectronic assembly as claimed in claim 17, wherein the stiffeningencapsulant layer is provided around outer edges of the microelectronicelement.